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王伶俐

系别: 微电子学院
职称: 教授 博导
职务:
办公室:  复旦大学张江校区微电子楼381室
电话: 5135 5336
E-mail: llwang@fudan.edu.cn
主页:
   
教育背景
   浙江大学物理系    本科学生并留校工作
   浙江大学电子工程系   硕士研究生
   英国爱丁堡?Napier大学工程学院   博士研究生
研究方向
课程教学
大二本科生必修课程 :“计算机软件基础”
大三本科生选修课程:“FPGA结构原理和应用”
研究生选修课程:“系统级可编程逻辑芯片设计”
学术兼职
IEEE/IET ICALIP(音频、语言与图像处理国际会议)International Program Committee member, Session Chair of “Software and Hardware Implementation:FPGAs” and “System-On-Chip”, 2008
The 7th INTERNATIONAL CONFERENCE ON ASIC (ASICON 2007), “VLSI design” Session Chair, Shanghai, China, October 26-29, 2007
The 6th INTERNATIONAL CONFERENCE ON ASIC (ASICON 2005), “VLSI design” Session Chair, Shanghai, China, October 24-27, 2005
指导学生参加"Altera杯"中国第五届研究生EDA电子设计竞赛,获团体金奖,清华大学,2005
第14届VLSI(超大规模集成电路)设计国际会议评审员 (14th International Conference on VLSI Design, IEEE Computer Society, Los Alamitos, California, U.S.A, 2001)。
科研项目
美国Synopsys公司:FPGA芯片设计和软件系统
智锐电子系统设计(上海)有限公司:面向可重构计算的FPGA软件算法开发,负责人
国家自然科学基金面上项目:量子计算电路的设计和综合,负责人
国防预先研究项目:自主FPGA技术开发研究
复旦青年科学基金:深亚微米FPGA的低功耗研究,负责人
国家大学生创新训练计划二类项目:FPGA时序收敛和码点调试工具,指导老师
教育部留学回国人员科研启动基金:量子计算电路的设计和优化,负责人
上海市浦江人才项目:抗辐射FPGA硬件电路与软件优化算法研究
上海市“科技创新行动计划”集成电路设计专项:国产自主知识产权FPGA的产业化应用和深入研发
论文著作
1.IEEE Asia Pacific Conference on Circuits and Systems,Singapore,Fast Conversion for Large Canonical OR-Coincidence Functions,,,1645-1648
2.计算机工程与应用,扩展Toffoli门及其在多输出电路设计中的应用,,Vol.45,No.2,88-91
3.电子与信息学报,FPGA通用开关盒层次化建模与优化,,第30卷,第5期,1239-1242
4.计算机工程,一种FPGA配置文件压缩算法,,Vol.34, No.11,260-262
5.International Conference on Solid-State and Integrated Circuit Technology,Framework of Converting C++ Class to Hardware,,,1823-1826
6.Integration, the VLSI Journal,Techniques for Dual Forms of Reed?Muller Expansion Conversion,,Vol. 41, No. 1,113-122
7.电子与信息学报,基于概率增益的电路划分算法,,Vol.29,No.11,2762-2766
8.计算机辅助设计与图形学学报,基于布通率的FPGA装箱算法,,Vol.19, No.1,108-113
9.The 49th IEEE International Midwest Symposium on Circuits and Systems(MWSCAS),A Delay Model for SRAM-Based FPGA Interconnections,,,
10.Journal of the Korean Physical Society,Analytic Investigation on Threshold Voltage of Fully-depleted Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect-Transistors,,Vol. 52, No. 6,1909-1912
11.11th IEEE International Conference Technology Proceedings,Search for the best Polarity of Fixed Polarity Reed Muller Expression base on QGA,,,343-346
12.International Symposium on Intelligent Information Technology Application,Zero-hardened SRAM Cells to Improve Soft Error Tolerance in FPGA,,,278-281
13.International Symposium on Intelligent Information Technology Application,Search for the best polarity of multi-output RM circuits base on QGA,,,279-282
14.International Conference on Solid-State and Integrated Circuit Technology,FPGA Interconnect Testing Algorithm Based on Routing-Resource Graph,,,2087-2090
15.International Conference on Solid-State and Integrated Circuit Technology,Extended Toffoli gate implementation with photons,,,575-578
16.International Conference on Solid-State and Integrated Circuit Technology,A Novel Packing Algorithm for Sparse Crossbar FPGA Architectures,,,2345-2348
17.International Conference on Solid-State and Integrated Circuit Technology,Efficient RM conversion algorithm for large multiple output functions,,,2300-2303
18.Japanese Journal of Applied Physics,Theory of Short-Channel Surrounding-Gate Metal?Oxide?Semiconductor Field-Effect-Transistors,,Vol. 46, No.4A,1437-1440
19.8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT),shanghai,FPGA Routing Architecture Optimization,,,1934-1936
20.8th International Conference on Solid-State and Integrated-Circuit Technology ,Shanghai,Methodology of the Design for Segments-Switchable Switch Blocks,,,1944-1946
21.8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT),shanghai,An Innovative Embedded Logic Analyzer Based SoC Verification Platform,,,1876-1879
22.IEE Proceedings Computers and Digital Techniques,Multilevel Logic Simplification Based on Containment Recursive Paradigm,,Vol.150, No.4,218-226
23.IEE Proceedings Computers and Digital Techniques,Exact Minimisation of Large Multiple Output FPRM Functions,,Vol.149, No.5,203-212
24.IEE Proceedings Circuits, Devices and Systems,Optimisation of Reed-Muller PLA Implementations,,Vol.149, No.2,119-128
25.IEE Proceedings Circuits, Devices and Systems,Multi-Code State Assignment for Low Power Sequential Circuit Design,,Vol.147, No.5,271-275
获奖情况
2007.01----获教育部科技进步二等奖“适用于数据通路应用的可编程逻辑器件及其软件系统”(第三完成人)
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